Items | Specifications |
| On-chip RAM | |
| Cache memory | - Instruction cache: 8 Kbytes
- Operand cache: 8 Kbytes
- 128-entry, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache
- Write-back, write-through, LUR replacement algorithm
- Cache lock function available (only for operand cache); ways 2 and 3 can be locked
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| CPU | - Renesas Electronics original SuperH architecture
- Compatible with SH-1, SH-2 and SH-2E at object code level
- 32-bit internal data bus
- Support of an abundant register-set
- Sixteen 32-bit general registers
- Four 32-bit control registers
- Four 32-bit system registers
- Register bank for high-speed response to interrupts - RISC-type instruction set (upward compatible with SH series)
- Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability
- Load/store architecture
- Delayed branch instructions
- Instruction set based on C language - Superscalar architecture to execute two instructions at one time
- Instruction execution time: Up to two instructions/cycle
- Address space: 4 Gbytes
- Internal multiplier
- Five-stage pipeline
- Harvard architecture
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Floating-point unit
(FPU) | - Floating-point co-processor included
- Supports single-precision (32-bit) and double-precision (64-bit)
- Supports data types and exceptions that conform to IEEE754 standard
- Two rounding modes: Round to the nearest and round to zero
- Handling of denormalized numbers: Flush to zero
- Floating-point registers
- Sixteen 32-bit floating-point registers (single-precision x 16 words or double-precision x 8 words)
- Two 32-bit floating-point system registers - Supports FMAC (multiplication and accumulation) instruction
- Supports FDIV (division) and FSQRT (square root) instructions
- Supports FLDI0/FLDI1 (load constant 0/1) instructions
- Instruction execution time
- Latency (FAMC/FADD/FSUB/FMUL): Three cycles (singleprecision), eight cycles (double-precision)
- Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six cycles (double-precision)
Note: FMAC only supports single-precision - Five-stage pipeline
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Interrupt controller
(INTC) | - Nine external interrupt pins (NMI, IRQ7 to IRQ0)
- On-chip peripheral interrupts: Priority level set for each module
- 16 priority levels available
- Register bank enabling fast register saving and restoring in interrupt processing
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Bus state controller
(BSC) | - Address space divided into five areas, each a maximum of 64Mbytes
- External bus width: 32-bit
- The following features settable for each area independently
- Bus size (8, 16, or 32 bits): Available sizes depend on the area.
- Number of access wait cycles
- Idle wait cycle insertion (between same area access cycles or different area access cycles)
- Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection and SDRAM
- PCMCIA interface
- Outputs a chip select signal according to the target area (CS assert or negate timing can be selected by software) - SDRAM refresh
- Auto refresh or self refresh mode selectable - SDRAM burst access
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Direct memory access controller
(DMAC) | - Eight channels; external request available for two of them
- Can be activated by on-chip peripheral modules
- Burst mode and cycle steal mode
- Intermittent mode available (16 and 64 cycles supported)
- Transfer information can be automatically reloaded
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Clock pulse generator
(CPG) | - Clock mode: Input clock can be selected from external input (EXTAL or CKIO) or crystal resonator (EXTAL/XTAL or USB_X1/USB_X2)
- Three types of clocks generated:
- CPU clock: 200MHz(regular specifications MAX), 133MHz(wide-range specifications MAX) |
| Power-down modes | - Three power-down modes provided to reduce the current consumption in this LSI
- Sleep mode
- Software standby mode
- Module standby mode |
Compare match timer
(CMT) | - Two-channel 16-bit counters
- Four types of clock can be selected (Pφ/8, Pφ/32, Pφ/128, and Pφ/512)
- Generates compare match interrupts
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Watchdog timer
(WDT) | - On-chip one-channel watchdog timer
- A counter overflow can reset the LSI
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Ethernet controller
(EtherC) | - MAC (Media Access Control) function
- Data frame assembly/disassembly (frame format conforming to IEEE802.3u)
- CSMA/CD link management (collision prevention and collision processing)
- CRC processing
- 512 bytes each for transmit/receive FIFO
- Full-duplex transmit/receive support
- Short packet/long packet transmit/receive - Conforms to the MII (Media Independent Interface) standard
- Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream
- Station management (STA function)
- 18 TTL-level signals
- 10/100 Mbps transfer rate adjustable - Magic PacketTM* (WOL (Wake-On-LAN) output)
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| Ethernet controller DMAC (EDMAC) | - CPU load reduced with the descriptor management method
- For transferring from EtherC receive FIFO to receive buffer x 1 channel
- For transferring from transmit buffer to EtherC transmit FIFO x 1channel
- 16-byte burst transfer improves the efficiency of system bus
- Supports single frame and multiple buffer
- Checksum receive data
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Stream interface
(STIF) | - 2 channel ports, link with A-DMAC
- Selectable from serial mode or parallel mode for each channel
- MPEG2-TS transfer mode, MPEG-PS transfer mode
- Support push type transfer and pull type transfer to each devices
- PWM timer output for external VCO control for each channel
- Common stream clock out for each channel. Stream clock in for each channel
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Serila sound interface
(SSI) | - Bidirectional serial transfer on two channels
- Support of various serial audio formats
- Support of master and slave functions
- Programmable generation of word clock and bit clock
- Multi-channel formats
- Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats
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USB2.0 host
/function module
(USB) | - Conforms to the Universal Serial Bus Specification Revision 2.0
- 480-Mbps, 12-Mbps, and 1.5-Mbps transfer rates
- Host and function can be switched
- Connect to several pheripheral devices via a hub when host is operating.
- Includes 8-Kbyte RAM as communication buffers
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SD host interface
(SDHI)
(H7671, SH7673 only) | - SD memory I/O card interface (1-/4-bits SD bus)
- Error check function: CRC7 (command), CRC16 (data)
- Interrupt requests
- Card access interrupt
- SDIO access interrupt
- Card detect interrupt - DMAC transfer requests
- SD_BUF write
- SD_BUF read - Card detection and write protection supported
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I2C bus interface 3
(IIC3) | - One channel
- Master mode and slave mode supported
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Host interface
(HIF) | - 1 kbyte x 2 banks: in total 2-kbyte buffer RAM
- The buffer RAM and the external device are connected in parallel via 16 data pins
- The buffer RAM and the CPU of this LSI are connected in parallel via internal bus
- The external device can access the desired register after the register index has been specified. (However, when the buffer RAM is accessed successively, the address is updated automatically.)
- Selection of endian mode
- Interrupt requested to the external device
- Internal interrupt requested to the CPU of this LSI
- Booting from the buffer RAM is enabled if the external device has stored the instruction code in the buffer RAM
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Serial communication interface with FIFO
(SCIF) | - Three channels
- Clock synchronous or asynchronous mode selectable
- Simultaneous transmission and reception (full-duplex communication)
- Dedicated baud rate generator
- Separate 16-byte FIFO registers for transmission and reception
- Modem control function (in asynchronous mode)
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Encryption function
(AES, DES, 3DES, MUGI TM**)
(SH7672, SH7673 only) | - Start encryption and decryption engine from both 2 channel of dedicated DMAC(A-DMAC) and CPU.
- With A-DMAC descriptor reading operation, possible to proceed continuous encryption/decryption supported by switching the source address (pointer of pre-processed data ) and by the each setting (algorithm of encryption and decryption, encryption/decryption selection, ECB/CBC/OFB, key, IV, etc.)
- Possible to proceed encryption and decryption by each block triggered by CPU.
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Massage authentication code generation function
(HMAC-SHA-1,
HMAC-SHA-224,
HMAC-SHA-256)
(SH7672, SH7673 only) | - With A-DMAC descriptor reading operation, generate various message authentication code and checksum linking with encryption and decryption processing
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User break controller
(UBC) | - Two break channels
- Addresses, data values, type of access, and data size can all be set as break conditions
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| High-performance user debugging interface (H-UDI) | - E10A emulator support
- JTAG-standard pin assignment
- Boundary scan support
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| I/O ports | - 86 general I/Os and 8 general inputs
- Input or output can be selected for each bit
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| Package | - P-LFBGA1717-256 (0.8 pitch)
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| Power supply voltage | - I/O: 3.3±(TBD)V, Internal: 1.2±(TBD)V
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| Operating frequency | - - 20 to ＋70 degrees C (regular specification product)
- - 40 to ＋85 degrees C (wide-range specification product)
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Americas
