SH7214, SH7216

Block Diagram
Pin Arrangement
Product Specifications
IBIS/BSDL

SH7214, SH7216 Product Specifications

Items	Specifications
On-chip memory	SH7216: ROM/1MB, RAM/128KB The writing to and erasion of flash memory by on-chip single power supply
CPU	Renesas Electronics original SuperH architecture 32-bit internal architecture General-purpose register architectur Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC（Reduced Instruction Set Computer）-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branch Instruction set based on C language Instruction execution time: Basic instructions execute in one state (5 ns/instruction at 200 MHz operation) Address space: Architecture supports 4 Gbytes On-chip Multiplier 32 x 32 → 64 multiply operations executed in two to five cycles 32 x 32 + 64 → 64 multiply-and-accumulate operations executed in two to five cycles Five-stage pipeline Harvard architecture
FPU (SH7216 only)	On-chip floating-point coprocessor Supports single-precision(32 bits) and double-precision(64 bits) Supports IEEE 754-compliant data types and exceptions Handling of denormalize numbers : Truncation to Zero Floating-point registers Sixteen 32-bit floating-point registers(single precision x 16 words or double-precision x 8 words) Two 32-bit floating-point system registers Supports FMAC(multiply and accumulate) instruction Supports FDIV(division) and FSQRT(square root) instructions Supports FLDI0/FLDI1(load constant 0/1) instructions Instruction execution times Latency(FMAC/FADD/FSUB/FMUL) : 3 cycles(single-precision), 8 cycles(double-precision) Pitch(FMAC/FADD/FSUB/FMUL) : 1cycle(single-precision), 6 cycles(double-precision) Five-stage pipeline
Operating mode	Operating mode Single-chip mode External bus expanded mode with on-chip ROM enabled Processing states Program execution Exception handling state Bus mastership release state Power-down modes Sleep mode Software standby mode Module standby mode
Clock Pulse Generator (CPG)	Clock mode: Input clock can be selected from external input (EXTAL) or crystal oscillator Five types of clocks generated: CPU clock: 200MHz(max) Bus clock: 50MHz(max) Peripheral clock: 50MHz(max) MTU2S clock: 100MHz(max) A/D converter clock: 50MHz(max) Power-down modes Sleep mode Software standby mode Module standby mode
Watchdog Timer (WDT)	One-channel watchdog timer Interrupt request
Interrupt Controller (INTC)	Nine external interrupt pins (NMI, IRQ7 to IRQ0) On-chip peripheral interrupts: Priority level set for each module Register bank enabling fast register saving and restoring in interrupt processing
User Break Controller (UBC)	Addresses, data values, type of access, and data size can all be set as break conditions Four break channels
Bus State Controller (BSC)	Address space divided into eight areas(0 to 7), each a maximum of 64 Mbytes a harvard The following features settable for each area independently Bus size (8 or 16 bits or 32bits) Number of access wait cycles Idle wait cycle insertion SDRAM support Auto refresh and Self refresh Burst access
Data Transfer Controller (DTC)	Data transfer independent of the CPU possible through peripheral I/O interrupt requests Transfer mode can be set for each interrupt factor (transfer mode set in memory) Multiple data transfers possible for one activating factor (chain transfer) Abundant transfer modes Normal mode/repeat mode/block transfer mode selectable Transfer unit can be set to byte/word/longword Interrupts activating the DTC requested of the CPU Interrupts can be generated to the CPU after completion of one data transfer Interrupts can be generated to the CPU after completing all designated data transfers
Direct Memory Access Controller (DMAC)	Eight channels : external request available for four channels of them Can be activated by on-chip peripheral modules Burst mode and cycle steal mode Intermittent mode available(16 and 64 cycle supported) Transfer information can be automatically reloated
Multi-Function Timer Pulse Unit2 (MTU2)	Non-overlapping 3-phase PWM waveforms output for inverter control Maximum 16-pulse input/output, 3-pulse input Selection of 8 counter input clocks for each channel Buffer operation settable for channels 0,3,and 4 Phase counting mode settable independently for each of channels 1 and 2 Cascade connection operation Automatic transfer of register data A/D converter conversion start trigger can be generated
Multi-Function Timer Pulse Unit2S (MTU2S)	Non-overlapping 3-phase PWM waveforms output for inverter control Operating at 80 MHz max. Maximum 8-pulse input/output, 3-pulse input Selection of 8 counter input clocks for each channel Buffer operation settable Automatic transfer of register data A/D converter conversion start trigger can be generated
Compare Match Timer (CMT)	Two-channel 16-bit timer Four types of clock can be selected
Serial Communication Interface (SCI)	Four channels Clocked synchronous or asynchronous mode selectable Simultaneous transmission and reception (full-duplex communication) supported Dedicated baud rate generator
Serial Communication Interface with FIFO (SCIF)	One channel Clocked synchronous or asynchronous mode selectable Simultaneous transmissin and reception(full-duplex communication) supported Dedicated baud rate generator Separate 16-byte FIFO registers for transmission and reception
Renesas serial peripheral interface (RSPI)	Clock synchronous mode serial communications Master mode or slave mode selectable Modifiable bit length, clock polarity, and clock phase A transfer can be executed in sequential loops Switchable MSB first/LSB first Maximum transfer rate : 10MHz Up to four slaves can be controlled in single master mode(depends on the PFC setting) Up to three slaves can be controlled in multi-master mode(depends on the PFC setting)
Universal serial bus (USB)	USB 2.0 full-speed mode(12Mbps) supported On-chip bus transceiver Srandard commands automatically processed by hardware Three transfer modes(control transfer, balk transfer, and interrupt transfer) 27 types of interface DMA transfer interface EP1 to EP9 : assigned to Bulk IN, bulk OUT, or Interrupt IN
(EtherC)	MAC (Media Access Control) function Data frame assembly/disassembly (frame format conforming to IEEE802.3u) CSMA/CD link management (collision prevention and collision processing) CRC processing 2K bytes each for transmit/receive FIFO Full-duplex transmit/receive support Short packet/long packet transmit/receive Conforms to the MII (Media Independent Interface) standard Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream Station management (STA function) 18 TTL-level signals 10/100 Mbps transfer rate adjustable Magic PacketTM* (WOL (Wake-On-LAN) output)
(E-DMAC)	CPU load reduced with the descriptor management method For transferring from EtherC receive FIFO to receive buffer x 1 channel For transferring from transmit buffer to EtherC transmit FIFO x 1channel 32-byte burst transfer improves the efficiency of system bus Supports single frame and multiple buffer
Controller area network (RCAN-ET)	CAN version : Bosch 2.0B active is supported Buffer size : 15 buffers for transmission/reception and one buffer for reception only One channel
I²C bus interface3 (IIC3)	One channel Master mode and slave mode supported
I/O port	102 general input/output pins, 8 general input pins
A/D converter	Two modules 12-bits, 8 channels Sampling can be carried out simultaneously on three channels A/D conversion request by the external trigger or timer trigger