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Improve operation performance by adding division instruction, bit operation
and other instructions.
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Realize 360 MIPS of real-time performance at 160 to 200MHz.
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A Superscalar architecture (5-stage pipeline) enables up to two instructions
to be executed simultaneously.
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Reduce the interrupt response time by using dedicated register banks for
interrupts.
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Reduce program code size by added new instructions.
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Americas
