SH-MobileR2R

MPU & MCU

SH-Mobile

Overview
Further Information

Overview

SH-MobileR2R is intended for use in IP security cameras, car navigation systems and personal navigation devices (PNDs) supporting the terrestrial digital TV broadcast standard and delivers enhanced performance, including the ability to play and record high-definition (1,280 × 720 pixels, abbreviated as HD) video.

Key Features

	(1)	Terrestrial digital TV broadcast support and HD video playback and recording
	(2)	Two camera module interfaces combined with VPU5F and JPU
	(3)	High operating frequency of 500 MHz for high-performance processing of tasks such as simultaneous two-screen display
	(4)	Full complement of high-performance peripheral functions for multimedia applications

Specifications

Product name	SH7724 (R8A77240D500BG)	SH7724 (R8A77240B500BB)
Operating temperature range	-40 to 85°C	-20 to 70°C
CPU core	SH-4A (with MMU)
Max. operating frequency	500 MHz
Max. processing performance	900 MIPS, 3.5 GFLOPS (at 500 MHz)
Cache memory	Primary cache: 32 Kbytes instruction/32 Kbytes data, separate Secondary cache: 256 Kbytes instruction/data, shared
Media data RAM	128 Kbytes
On-chip RAM	16 Kbytes
External memory	Dedicated controller for DDR2/MobileDDR Connection via 32-bit bus, max. operating frequency: 166.7 MHz	Dedicated controller for MobileDDR Connection via 32-bit bus, max. operating frequency: 166.7 MHz
	Local bus controller Support for connection to ROM, SRAM, PCMCIA, etc., connection via 16-bit or 32-bit bus, max. operating frequency: 83.3 MHz
Main on-chip peripheral functions	Video I/O (camera module direct connection interface) Video image processing functions (color conversion, image enlargement/reduction, filtering) Image blending function VPU5F (H.264, MPEG-4, VC-1) JPU(JPEG encode, decode) Video output unit LCD controller with support for 24-bit TFT color LCD panels 2-D graphics accelerator Sound processing unit (24-bit dedicated audio DSP) USB 2.0 Host/Function controller (with high-speed mode support) x 2 channels ATAPI interface TS interface DMAC × 12 channels FIFO serial interface × 1 channel 32-bit timer unit × 6 channels 32-bit compare-match timer × 1 channel 16-bit timer pulse unit × 4 channels Realtime clock × 1 channel Watchdog timer × 1 channel I²C bus interface × 1 channel Key scan interface Asynchronous/clock-synchronous serial interface × 6 channelsI rDA interface (with v1.2a support) MMC4.2-compliant NAND interface SD memory/SDIO card interface × 2 channels Ethernet MAC (10M/100M bps) H-UDI on-chip debug function
Power-down (low-power) modes	Sleep mode Standby mode R standby mode U standby mode
Package	449-pin BGA (21 mm × 21 mm, 0.8 mm pin pitch)	441-pin POP-compatible BGA (14 mm × 14 mm, 0.5 mm pin pitch)