Multi-Core

Our ubiquitous computing society is ever evolving, and with it, the functionality and performance of our electronic devices and equipment. Naturally, microcontrollers, which are the backbone of the functionality of those devices and equipment, are thus required to improve functionality and performance at a even higher rate. Conventionally, higher performance was typically achieved by refining manufacturing processes to improve level of integration and operating speed. However, this method requires finding solutions for increased leak current and other issues, making it unable to keep pace with the current rate of evolution.
Renesas Electronics responded by working on multiple cores in addition to process refinement. SuperH products were created by integrating multiple CPU cores on a single chip to enable advanced processing without an increase in operating frequency.
The result was SH2A-DUAL and SH4A-MULTI.
The first SH2A-DUAL products are equipped with two SH2A-FPU cores, and have a maximum operating frequency of 200 MHz. They are upward compatible with SH-2A and SH-2 CPU cores at the instruction set level, allowing programs that were developed using SH-2A and SH-2 to be used in a multi-core system.
The first SH4A-MULTI products are equipped with two SH-4A cores which support multi-core configurations, and have a maximum operating frequency of 533 MHz. They are upward compatible with SH-4A at the instruction set level, allowing programs that were developed using SH-4A to be used in a multi-core system.

The first advantage is a great reduction in number of peripheral devices. The two cores can share memory resources, so the number of memory devices can also be reduced. Furthermore, space-saving benefits from shared I/O and bus can also be expected.

Part of the memory can be shared. Data can be transferred via this communication memory area. Interrupts between the two CPUs are also possible; for example, sending an interrupt from one CPU to the other to notify of parameter transfer.
*However, it is possible for direct manipulation from an application to cause malfunction and fatal damage to the system. Therefore, it is recommended that data transfer always be performed using the communication functions provided by an AMP OS, such as HI7200/MP.

Interrupts between CPUs
One CPU sends an interrupt to the other CPU to notify of parameter transfer, etc.
(Supported by special hardware)

Parameter transfer
Send and receive parameters by transferring a copy through the communication memory area.
(Included in URAM of each core)

The SH2A-DUAL and the SH4A-MULTI greatly decrease current consumption compared to equivalent performance by a single core. Therefore, current consumption can be reduced while achieving higher performance. This allows more freedom in terms of integration of other IPs, package selection, and cost.

1. CPU suitable for high-performance embedded devices
   Supports instructions with high code efficiency, as well as faster interrupt response speed due to register bank.
2. Uses a 2-way superscalar that includes FPU instruction
   Performance surpasses DSP in certain areas.
3. Guarantees processing response cycle and has high-speed response
   Stores programs that require real-time characteristics in the on-chip RAM area.

• Each core maintains its own cache memory and URAM
• MLB (Multi Layer Bus）
  Through the MLB, the SH-2A Dual enables independent parallel bus access for bus masters such as CPU0, CPU1, and DMAC, preserving latency in access to the slave module.

• Each core maintains its own cache memory
• On-chip snoop controller (SNC) for cache coherency control. Updated cache data is handled among CPU cores via the SNC, maintaining cache coherence among each core. As this is a different route from the internal SuperHyway bus, cache data can be handled without interfering with data transfer on the SuperHyway bus.