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- Overview
- Further Information
| SuperHyway overview |  |
| The SuperHyway Bus™ on-chip interconnect comprises a set of
tools that enable a developer to build efficient, high performance SoC
products. The SuperHyway is VSIA 2.1 Compliant™. For more details please visit www.vsia.org The SuperHyway has been designed to address the requirements of SoC developers: |
|
| Demand |
Solution |
| Must meet latency, bandwidth, scheduling | A unified bus architecture supporting three interface classes |
| Accommodate multiple bus masters | High-end bus supports split, pipeline, and out of order accesses |
| Must support high-speed and low speed IPs |
Bus-master arbitration and data packet priority handling schemes |
| Non-intrusive and visible debug feature | Real time trace and intelligent event detections |
| Facilitate development of complex systems | Deliver interconnection generator, IP verification tools and templates |
| Supports IP from multiple sources | AMBA, CoreConnect, VSI Alliance |
| Bus type | Description |
| Type 1 |
Not available |
| Type 2 |
Not available |
| Type 3 |
For CPU and dedicated engines up to 1024 bits, composite transactions including cache purge, performance optimizations include out of order execution. A typical implementation would be 64-bit at 200MHz. |