CPU cores

Debug Support

Time-to-market is a critical area for SoC developers and debug support is one of the most important factors in delivering an SoC system on schedule. Renesas offers support in a number of areas from development through to production and field support.

JTAG
A JTAG port is part of the SoC design and is not delivered as part of the SuperH CPU core, however SuperH based SoC devices can fully implement designs to the JTAG standard.

Memory test
SuperH based SoC devices can be implemented with BIST (built-in self test) for testing on-chip memories and caches.

Debug interfaces
All CPU based SoC products require a debug port to enable both software and hardware debugging of the SoC device and this port may also be used in the final product during production test or to make firmware changes to products in the field. The debug ports are available as licensable synthesizable IP.

Renesas works extensively with 3rd parties to ensure a wide range of tools are available. One of the key factors in enabling this support is defining a standard Debug Interface.

SH-4 family debug
For the SH-4 family Renesas has adopted the UDI/AUD debug port used for their SuperH based products which is widely supported by 3rd parties. This debug port is implemented with 2 blocks in the CPU core:

• EMU contains the interface logic to connect an debug module (e.g. MicroProbe) to the SoC and enables programs to be download, run and debugged.
• ASEM is a 1KB memory used for holding the debug program.

The SH-4 family debug functionality (the Emulation Support Package) is delivered with the cores but may be omiited by customer from their SoC designs where small size or low pin count are important factors.

More detail can be found in the Documentation section on this website

SH-5 family debug
For the SH-5 family Renesas has developed the SHdebug port that enables users to debug the CPU and SuperHyway interconnect. The SHdebug port is included in all SH-5 hard core products today.

The SHdebug port provides a low pin count (11 pins) high bandwidth port for connection to a range of software debug tools. Alternatively a JTAG interface may be used where pin count is critical but the bandwidth and performance will be lower.

Key features of the SHdebug port:

• 16 MB of memory space is mapped to the debug port enabling ROMless development of an SH-5 SoC.
• A bus analyzer enables the trigger points from the SuperHyway bus as well as the SH-5 CPU.
• Watchpoints can be set on events such as instruction address, operand address and PC value.
• Fast printf: a memory mapped register can be used to dump trace data or timing information.
• Bus analyzer: can be used to with CPU watchpoints to generate sophisticated filtering events.
• Performance counters: used to counter arbitrary events from CPU or bus analyzer.
• Chain latches: enable watchpoint hits to enable or disable any other watchpoints.
• Trace facilities in conjunction with software debug tool using a variable size trace buffer up to 64MBytes.

More detail can be found in the Documentation section on this website

Software debuggers
Software debug tools are included within the toolsets provided by Renesas and third parties. For example the SuperH tools are based on the GNU tools and include the GNU debugger GDB.

Further detail on SuperH debug tools are contained with the AEDK page on this website.

Further details on third party tools can be found on the Partner Page on this website.