CPU cores

CPU roadmap

Renesas delivers a comprehensive range of 32 and 64-bit RISC CPU cores for integration into SoC devices in technologies including 0.18µm, 0.13µm and 90nm. Each family, such as the 32-bit SH-4, comprises a range of both synthesizable and hard macro options.

* DMIPS = Dhrystone 2.1

Renesas has focused on the following key areas in response to the needs of our licensees:

Integrated RISC and DSP performance
Many SoC designs today integrate a RISC and DSP core. This approach requires intimate knowledge of the RISC and DSP architectures and requires two separate memory systems. With the multimedia orientated instruction sets in the SuperH architecture these designs can now be delivered with a single SuperH architecture CPU core.

Multimedia performance
With the MAC/MUL, vector FPU and SIMD capabilities SuperH based SoC products can deliver programmable multimedia solutions for systems integrating video, audio, speech and graphics functions for MPEG4, MP3, H26x and G7xx.

Software compatibility
Renesas delivers upward software compatibility through its 16-bit SHcompact instruction set. Furthermore Renesas delivers a standard set of peripherals including clocks, timers, serial port and interrupts which provide a standard environment for 3rd parties porting their software. FPU code is binary compatible across the SH4-200 group and SH5-100 group. This unique approach reduces costs and time-to-market for both 3rd parties and licensees.

Power and die size
SuperH cores are the most efficient on the market, focused on delivering MIPS/MHz, MIPS/watt and MIPS/mm².

On-chip interconnect
Bottlenecks in SoC device performance are often concerned with the on-chip interconnect. Renesas delivers the SuperHyway Bus which is a scalable high bandwidth, low latency interconnect that can be customized by the SoC designer to suit their specific requirements. The SuperHyway supports interfaces to peripherals designed to other buses such as AMBA.

Debug support
In order to minimize time-to-market Renesas makes available synthesizable on-chip debug ports that licensees can integrate in their SoCs and ensure compatibility with 3rd party tools.

IP delivery
Renesas has developed a set of Design Kits for the efficient delivery of IP for evaluation, SoC integration and software development. See Design Kits